AMD Zen 6 Benchmark Leak: 10-Core Medusa Point Outperforms Current Strix Point Chips

Leaked benchmark results for AMD's next-generation Ryzen processors indicate a significant performance jump over the current Zen 5 lineup, even at this early engineering-sample stage. A newly surfaced Geekbench result for AMD's Medusa Point chip, built on Zen 6 architecture, offers one of the clearest early looks yet at what the next generation of Ryzen hardware could deliver.

The leaked result shows a 10-core Medusa Point sample scoring around 3200 points in single-core performance and around 15000 points in multi-core performance. Compared to the equivalent 10-core Strix Point chip, it represents a 29% gain in single-core performance and a 22% gain in multi-core performance.

Medusa Point is expected to target laptops and similar systems in the 28W to 45W power range rather than desktop-class power budgets, making these early gains particularly notable given the platform's power constraints.

The Reported 2GHz Clock Speed is Likely Inaccurate

The benchmark result lists a clock speed of just 2GHz, a figure worth treating with real skepticism. Assuming the result itself is genuine, a processor beating its predecessor by around 20% in multi-core performance while running at less than half the clock speed of competing chips is not realistic.

AMD has already indicated that Zen 6 architecture brings significant improvements to specific workloads, including integer 8 operations, and Geekbench results can reflect a mix of workloads that don't map directly onto typical usage. Even accounting for that, a genuine 2GHz result producing these numbers would be extraordinary.

A separate, later leak for what appears to be the same chip showed a boost clock closer to 3.4GHz, which would bring the actual IPC gain down to a more modest, though still meaningful, range of roughly 7% to 18% rather than the inflated 20-plus percent figures implied by comparing scores at the misreported 2GHz clock.

Cache and Instruction Set Details

Along with the main performance numbers, the leak includes information on how the cache is configured, which further confirms what we already knew about the Zen 6's specs. The chip has 32MB of L3 cache, which is much more than the 24MB on Strix Point, and 10MB of L2 cache, matching the current 10-core Strix Point parts.

The leak also says that FP16 AVX-VNNI support is first seen on a Zen 6 chip. This means that AI and machine learning tasks will be able to use more low-precision computing power. AMD hasn't officially said how many cores desktop Zen 6 processors will have, but most experts think the number of cores will increase by about 50% across the board.

As of now, the most powerful Ryzen desktop chip has 16 cores. Zen 6 is likely to boost that to 24 cores and 48 threads at the top end. Taking into account gains in certain niche workloads, Zen 6 is projected to deliver overall IPC improvements of about 10% to 15%.

Separate benchmark data, covering roughly a month prior to this leak, offers a look at Zen 6-based EPYC server performance at the rack level. That data compares a 256-core EPYC Venice processor against the current 192-core EPYC Turin, measuring normalized rack-level system performance within a 100-kilowatt power budget, using a competing accelerator platform as the performance baseline.

AMD has confirmed that EPYC Venice will launch before consumer Ryzen Zen 6 processors.

Turin already shows a substantial performance advantage over the baseline across a range of workloads, and Venice's higher core count suggests further gains once it becomes available. AMD has described the architecture as continuing its x86 leadership while remaining optimized for standard, standalone x86 workloads.

An exact release date for desktop Ryzen Zen 6 processors has not been confirmed, though early next year appears to be a reasonable expectation based on current information. RDNA 5 graphics architecture is expected to follow, likely in the second half of 2027, suggesting AMD is planning a staggered rollout with processors launching first and GPUs arriving afterward.