AMD Zen 6 Medusa Point Leak Reveals 32MB L3 Cache and Major FP10 Platform Shift

AMD's next-gen mobile CPUs are now on the road from roadmap to silicon. A recently leaked Geekbench result from an engineering sample (internally codenamed "AMD Plum-MDS1") provides the first reliable insight into the potential of Zen 6, code-named Medusa Point, for future mobile systems.

As with all engineering samples, the benchmark results mean nothing. But the configuration reveals significant architectural evolution, rather than an incremental update.

The engineering sample leak reveals a 10-core/20-thread design with a 2.40 GHz base clock, 10 MB of L2 cache, and a rather impressive 32 MB of L3 cache.

The L3 cache immediately sets this chip apart from existing Zen 5 mobile chips.

The highest L3 in comparable power envelopes is 24MB (Ryzen AI 9 365). The 32MB L3 cache is not an incremental increase, but a fundamental shift, and likely reflects changes in the core complexes and memory hierarchies. Such increases in cache usually mean a rearchitecting of data flow to cores, which affects latency-critical applications.

This is important for mobile gamers and power users. Increasing the shared cache size means there's less need to go to system memory, resulting in more consistent performance in CPU-limited gaming and better performance in workloads that benefit from fast data reuse. 

This is particularly important in modern game engines and productivity software, which are less tolerant of latency bottlenecks than previous generations.

The Geekbench listing shows the clocked chip as running at very low validation speeds, at around 2 GHz. By itself, that makes all of the performance numbers meaningless.

Validation chips are not built to work fast. They are designed to test basic functionality, thermals, and electrical performance. Speeds are purposely low, and the software is often unfinished. Using benchmark results from this stage is a significant misinterpretation of early silicon use.

The leak is of value only for the hardware. The signal is in the structure, not the numbers.

As significant as the platform around the chip. The leak links Medusa Point to the new FP10-BGA package, rather than the current FP8 platform, on which today's mobile designs are based.

Such a socket/package shift implies more than just a change in compatibility. It means new power management, memory interfaces, and board-level design, allowing laptop vendors to start fresh.

This type of transition often enables more efficient power scaling, the integration of new memory technologies, and better thermal design in thin-and-light devices.

For the ecosystem, FP10 is a fresh start. It allows AMD to scale beyond the limits of FP8 as mobile workloads grow in complexity and embrace AI acceleration.

This preview of Zen 6 Medusa Point is not a performance preview but an architectural sneak peek.

The shift to 32MB L3 is the most visible sign that this is a next-generation part, rather than a Zen 5 variant. It's a signal that, when paired with a move to FP10, points to a shift in AMD's mobile strategy.

That strategy is more important given Intel's forthcoming mobile processors, as efficiency, latency, and platform integration are equally important as raw performance.

For the time being, the verdict is clear. Don't worry about the benchmark results; listen to the silicon. Zen 6 is poised to be a generational leap for AMD's mobile CPUs, and this leak is the first real clue.