Future of AMD CPUs: Zen6 Setting the Stage for Zen7 and Beyond

Zen6 is shaping up to be an absolute juggernaut of a processor. Not just because of rumors, but because AMD's official disclosures about this architecture indicate it's going to be something very special. And indeed, it needs to be, especially with Intel's increasing competition. Intel's upcoming Nova Lake, with up to 52 cores and a dual-tile BLLC configuration, will reportedly feature 144MB of cache per tile, totaling 288MB on the processor. That is impressive.

However, the latest rumors from AMD suggest that it intends not only to match but also potentially exceed that, combined with numerous other Zen6 improvements, such as drastic IPC increases, dual memory control, and more.

Back in March of this year, Zang Xho Hong leaked an interesting detail indicating that the desktop non-X3D maximum is 48MB*2. Each CCD is expected to feature 48MB of L3 cache. This aligns with what we know about Medusa, which is expected to be Ryzen for desktop and mobile with up to 12 cores.

That represents a 50% increase in the number of cores. With Zen5 offering 32MB of L3 cache for 8 cores, it logically follows that AMD must increase L3 cache for Zen6 to ensure those cores have sufficient on-chip cache.

HXL later suggested that AMD would match Intel's Nova Lake cache structure, with a single CCD offering 144 MB and a dual CCD offering 288 MB.

AMD would reach these numbers through 48MB of L3 plus 96MB of X3D cache per CCD. Multiplying by 2 yields the full 288 MB.

This rumor is intriguing for another reason. Intel's dual-tile Nova Lake architecture has encouraged speculation about AMD's own dual-CCD X3D launches. For Zen5, AMD is rumored to release a 9950X3D2 with two CCDs, each benefiting from V-Cache. Zen6 appears to be designed around this strategy from the start.

If so, you and we won't need to wait months for a 2-CCD X3D variant to arrive—Medusa may launch with it. This could be a good reason to wait for Zen6 if you haven't already played Zen5.

Moore's Law Is Dead also talked about a possible 192MB X3D setup with stacked dies, which would be one X3D cache on top of another X3D cache, plus a regular L3. This would probably cost a lot and be aimed at data-center or halo-tier products instead of regular buyers. Still, if Nova Lake proves highly competitive, AMD could choose to bring such a product to consumers.

Zen6 will include major architectural changes. AMD is completely redesigning how schedulers work for integer units. On Zen5, there is a single central scheduler, but on Zen6, it will be split into six separate schedulers.

This could improve power efficiency and workload distribution, and prepare the architecture for future enhancements in Zen7. Both AMD and Intel are clearly laying the groundwork for years of architectural evolution.

Another major rumor concerns a dual IMC design. Lmus (Yuri Bubbly), known for hydrotuning software, hinted at big IMC improvements. We can't say for sure that this is true, but their history makes it more likely. We think clock speeds will reach 6.2-6.3 GHz. Some high-end lab samples with unusual cooling might reach 7 GHz. Still, regular consumer silicon probably won't.

It's still hard to guess how much IPC will go up. We wouldn't be surprised by 10%, but we think 15% is more realistic. But it gets hard to report performance advances since some sources include clock-speed estimations in their IPC estimates and some don't.

Zen6 going to a 2nm technology provides AMD more area to work with, and given the big changes we've previously talked about in the architecture, 10–15% seems fair.

AMD has also published numbers that show a performance and efficiency boost of more than 70% with a 1.3x increase in thread density. Several things affect this value, such as thread count, power efficiency, and frequency scaling, it can't be directly compared to IPC. Still, such gains cannot be achieved solely through frequency and core count, reinforcing expectations that Zen6 will be a major advancement.

The main challenge Zen6 may face is Nova Lake. We currently expect Zen6 to have the edge in single-thread performance.

At the same time, Intel may take the lead in multi-threaded workloads. But uncertainty remains because the final clocks aren't known, and all available information is based on rumors.

Intel's U-BLLC cache versions should perform well in gaming. However, Intel faces a familiar issue: yet another new platform. AMD sticking with AM5 is a significant advantage. There is some debate about whether Zen7 will remain on AM5 or transition to AM6.

If AM6 launches, it will likely be accompanied by standards such as DDR6. Considering current memory prices—driven largely by data-center demand—it's unclear how quickly DDR6 would reach consumers.

If you're on an older platform such as AM4, you may be wondering whether it's worth upgrading or waiting. With memory prices currently inflated, it will be interesting to see how the market develops before Zen6 arrives. We expect memory supply to improve either through increased production or a potential price correction.